Apr 28, 2025·8 min
ASML and EUV: Why Lithography Became Chipmaking’s Gatekeeper
A clear, non-technical guide to how ASML’s EUV lithography tools became essential for cutting-edge chips, and why the whole industry depends on them.
A clear, non-technical guide to how ASML’s EUV lithography tools became essential for cutting-edge chips, and why the whole industry depends on them.
When people say “leading-edge” chips, they’re usually talking about the most advanced manufacturing processes: smaller features printed on silicon, higher transistor density, and better power/performance within the same battery or cooling budget. That’s how phones get faster without getting hotter, and how data centers do more work per watt.
ASML matters because it sits at a step that’s unusually hard to route around.
Lithography is the stage where patterns are projected onto a wafer—patterns that ultimately become transistors and wiring. If you can’t print the required patterns accurately enough, you can’t manufacture that generation of chips at scale.
So “gatekeeper” doesn’t mean ASML controls the entire semiconductor industry. It means that, at the frontier, progress depends on access to a particular capability that very few players can provide—and today that capability is concentrated in ASML’s most advanced lithography tools.
A few factors explain why ASML is so frequently in the spotlight:
This post focuses on concepts you can trust: what lithography is, why EUV was such a leap, and why the chip supply chain became sensitive to these tools. We’ll avoid hype and “magic” explanations and instead emphasize the practical constraints that make lithography a real bottleneck at the frontier.
Think of lithography as printing incredibly tiny patterns onto a silicon wafer using light. Those patterns define where transistors, wires, and contacts will later exist. If the “print” is even slightly off, a chip can lose performance, burn more power, or fail entirely.
Lithography is a repeated cycle used to build a chip layer by layer:
Coat resist: The wafer is covered with a light-sensitive material called photoresist.
Expose: Light shines through a photomask (a glass plate with the pattern). The lithography tool projects that pattern onto the resist, like a precision projector.
Develop: The exposed resist is chemically developed so parts wash away, leaving a patterned resist “stencil.”
Etch or deposit: Using the resist stencil, the fab either etches material away or deposits new material in the right places.
Repeat: A leading-edge chip can require dozens (often hundreds) of these loops across many layers.
Smaller transistors aren’t just “smaller drawings.” They demand tighter alignment between layers, cleaner edges, and less variation across an entire wafer. Lithography accuracy strongly influences how small and complex the final design can be—and how many good chips (“yield”) come off each wafer.
Lithography is only one part of semiconductor manufacturing—materials, deposition, etch, packaging, and testing all matter—but it’s often the hardest bottleneck because it sets the foundational pattern every other step must follow.
Chip progress is often described as “making transistors smaller.” The hidden constraint is that you also have to draw smaller shapes on silicon. At a high level, lithography follows a simple rule of thumb: the shorter the light’s wavelength, the finer the detail you can print.
If you try to print extremely tiny lines using relatively “long” light, the edges blur—like trying to write with a thick marker on graph paper. For years, the industry extended DUV lithography by improving lenses, light sources, and materials. Those improvements mattered, but they weren’t unlimited.
Engineers used clever techniques—better lens designs, tighter process control, and computational methods that pre-distort mask patterns so they print correctly on the wafer. These methods helped, but as features shrank, tiny errors that used to be tolerable became deal-breakers. Eventually, you can’t “optimize” your way past physics: diffraction and process variation start to dominate.
When a single exposure couldn’t reliably print the needed features, fabs adopted multi-patterning—splitting one layer into multiple mask-and-exposure cycles.
Multi-patterning kept nodes moving forward, but it turned lithography into a major bottleneck. More steps meant higher cost per wafer, longer cycle times, and tighter yield management. That growing burden is a big reason the industry pushed for a new wavelength and approach—setting the stage for EUV.
Deep ultraviolet (DUV) lithography uses 193‑nanometer light to print patterns onto a wafer through a photomask, using a light‑sensitive coating (photoresist). For years it was the workhorse of semiconductor manufacturing—and it still is. Even the most advanced fabs rely on DUV for many layers where features are larger or less critical, because the tools are fast, proven, and comparatively affordable.
A major upgrade to DUV was immersion lithography. Instead of exposing the wafer through air, the tool fills the tiny space between the lens and wafer with ultra‑pure water. That water bends light more than air, letting the system focus smaller features—like using a better “magnifying medium” to sharpen detail.
Immersion extended DUV much further than many expected, but it didn’t change the underlying reality: 193 nm is still a relatively “large” wavelength when you’re trying to draw extremely small transistor features.
To keep shrinking with DUV, chipmakers leaned heavily on multi-patterning—splitting one intended layer into two, three, or even more exposures and etch steps.
That works, but it carries clear costs:
Extreme ultraviolet (EUV) lithography uses much shorter 13.5‑nanometer light, which can print fine features in fewer passes. The appeal was simple: replace “many complicated DUV steps” with “fewer, more direct exposures” for critical layers.
EUV wasn’t adopted because it was easy—it wasn’t. It was adopted because, at the leading edge, the DUV multi-patterning path was becoming too slow, too costly, and too risky to keep scaling at pace.
EUV (extreme ultraviolet) lithography uses much shorter-wavelength light than “deep ultraviolet” (DUV) systems. Shorter wavelength matters because it can print smaller features more directly—think of it as a finer “pen” for drawing the most demanding chip patterns.
An EUV tool isn’t just a brighter lamp. It’s a carefully choreographed chain of subsystems:
All of that makes EUV tools expensive to build, expensive to maintain, and hard to scale in volume.
Before EUV, fabs often needed multiple exposures and complex multi-patterning with DUV to create fine features. For certain critical layers, EUV can reduce the number of patterning steps—saving time, lowering risk of alignment errors, and improving overall yield.
EUV doesn’t simplify an entire fab by itself. You still need advanced photomasks, finely tuned photoresist chemistry, precise process control, and complementary steps (etch, deposition, inspection). EUV helps on key layers, but chipmaking remains a tightly coupled end-to-end challenge.
An EUV “machine” is less like a single piece of equipment and more like a tightly orchestrated factory cell. It has to generate EUV light, shape it with near-perfect optics, move silicon wafers with nanometer precision, and constantly measure and correct itself—all while running day and night.
Light source: EUV light is created by firing high-power lasers at tiny droplets of tin to form a hot plasma that emits EUV radiation. Turning that bursty, messy physics into a stable, usable beam is a major engineering challenge.
Mirrors, not lenses: EUV is absorbed by most materials (including glass), so it can’t be focused with traditional lenses. Instead, the beam bounces through a chain of ultra-smooth, multilayer mirrors inside a vacuum environment.
Wafer stage and motion control: The wafer must scan under the patterning optics at high speed while staying aligned within a few nanometers. Precision mechatronics, vibration control, and thermal management become just as important as the light itself.
Mask handling and cleanliness: The photomask (reticle) carries the pattern. Handling it without particles and keeping everything contamination-free is critical, because EUV is sensitive to tiny defects.
Even if the hardware is world-class, the tool only earns money when it prints wafers reliably. EUV systems rely on metrology sensors to measure focus, alignment, and drift, plus software to correct errors in real time and manage thousands of operating parameters.
That’s why uptime and consistency matter as much as raw resolution. A small drop in availability can translate into a large loss of wafer output for a leading-edge fab.
EUV tools take a long time to install and qualify. They require cleanroom integration, careful calibration, and ongoing maintenance—often with dedicated field teams and regular replacement of consumable components. Buying the tool is only the start; operating it becomes a long-running partnership between the fab and the tool vendor.
ASML’s EUV tool isn’t a single “magic box.” It’s the end result of a tightly choreographed ecosystem of specialists—many of whom are world-class in a niche so narrow there may be only one credible supplier.
At a high level, EUV depends on:
Each subsystem is difficult on its own. Making them work together reliably, day after day, is the real feat.
Chipmakers don’t buy “EUV capability.” They buy consistent results: predictable image quality, stable uptime, known maintenance cycles, and a process window engineers can trust.
That takes years of shared tuning across ASML, suppliers, and customers: aligning specifications, fixing edge cases, tightening tolerances, and building feedback loops from real fab conditions back into design and manufacturing.
Even if demand spikes, EUV output can’t be doubled like ordinary industrial equipment. You need trained technicians, ultra-clean assembly, long-lead parts, exhaustive testing, and a global service organization to keep tools running. Expanding any one of those constraints takes time.
Because the supply chain is specialized and co-developed, switching providers isn’t like swapping brands. The accumulated know-how, qualified suppliers, and service infrastructure create a compounding advantage—making it hard for a second EUV ecosystem to appear quickly.
The main buyers of EUV systems are the handful of companies pushing the most advanced chips: TSMC, Samsung, and Intel. They run leading-edge fabs where small gains in transistor density, power use, and performance translate directly into better phones, GPUs, CPUs, and AI accelerators.
An EUV tool isn’t something a fab orders when demand spikes. Foundries plan years ahead because the decision is tied to the entire factory: building layout, cleanroom utilities, vibration control, contamination rules, and the process flow around the scanner.
In practice, they’re coordinating three moving parts at once:
Miss the alignment and you can end up with an expensive machine waiting on the building—or a new fab waiting on a machine.
Because EUV capacity is finite, access influences which companies can ramp new process generations smoothly, how quickly they can offer leading-edge production to customers, and how confidently they can commit to future nodes.
If a foundry can’t secure enough tools (or can’t run them at the needed uptime), it may need extra patterning steps or accept slower ramps—both of which raise cost and risk.
EUV scanners demand continuous tuning and upkeep. Field service engineers, spare parts logistics, software updates, and fast troubleshooting are part of the package. For fabs, the long-term dependency isn’t only on the tool itself, but on the support network that keeps it producing wafers day after day.
Lithography tools—especially EUV—aren’t just expensive pieces of factory equipment. They can effectively determine which regions can manufacture the most advanced chips at scale. That makes them a strategic chokepoint: limit access to leading lithography, and you can slow progress in everything built on top of leading-edge chips, from data centers and smartphones to industrial systems.
Unlike many parts of the semiconductor supply chain, top-tier lithography is highly concentrated. The number of companies that can build cutting-edge tools—along with the specialized components they require (optics, light sources, precision stages, materials)—is small. When capability is scarce and hard to replicate, governments treat it less like ordinary trade and more like strategic infrastructure.
Export controls are one way states try to manage that risk. In general terms, these rules can restrict shipment of certain technologies to specific destinations or end uses. The details—what is controlled, which performance thresholds matter, and what licensing is required—are set by governments and can evolve over time.
For chipmakers and suppliers, changing rules can reshape investment decisions quickly:
The practical result is that geopolitics can influence not only where chips are made, but also how fast new nodes reach volume production.
Because regulation can change, the safest approach is to follow official government publications, regulator guidance, and company filings rather than rumors. If you track this topic over time, revisit announcements as they’re issued and note how definitions and thresholds shift.
EUV tools are expensive for reasons that go beyond “advanced tech.” They’re built from ultra-precise parts (optics, stages, vacuum systems) that must align at extreme tolerances, and many of those parts can’t be sourced like standard industrial components.
First, manufacturing volumes are low. These machines aren’t produced by the tens of thousands; each one is closer to a bespoke industrial project than a mass-market product.
Second, the testing and calibration burden is huge: every subsystem has to work together at nanometer accuracy, and verifying performance takes time, specialized equipment, and highly trained teams.
That combination—precision + low volume + long test cycles—pushes unit costs up even before a tool ships.
For a chipmaker, the real question is: how many good wafers can this tool help produce, and how reliably?
Total cost of ownership typically includes:
A tool that’s “cheaper” but less available can end up being more expensive per chip.
Leading-edge capacity is constrained by how many lithography steps can be run per day. If EUV tool deliveries slip, or uptime falls, fabs may not hit planned wafer output. That pushes up wafer costs indirectly: fixed costs are spread over fewer wafers, and high-demand customers compete for limited slots. The result can show up later as higher chip prices—or simply fewer devices available.
Even with enough tools, progress depends on materials (photoresist and masks), design software and IP, and manufacturing skill (process control, yield learning). EUV is a gate, but it’s not the whole road.
High-NA EUV is the next major upgrade to EUV lithography. “NA” (numerical aperture) measures how much light the optics can collect and focus. Higher NA can project finer details onto the wafer—similar to using a sharper, higher-quality lens.
The goal is straightforward: print smaller features more cleanly, with fewer complex multi-patterning steps.
Even with better optics, several hard problems remain:
High-NA EUV will likely be adopted first where it pays off most—at the smallest, most expensive layers of leading-edge chips. For many other layers, today’s EUV and even DUV lithography will remain economically attractive.
That means fabs will run mixed tool fleets for a long time: High-NA for the tightest patterns, “standard” EUV for broad production, and DUV for less critical layers. This isn’t a switch to a single new machine; it’s an incremental reshaping of process flows.
New lithography generations require co-development across resists, masks, metrology, and process recipes. Even after the first tools arrive, reaching stable, high-volume manufacturing typically takes multiple years of iteration—especially at scale.
If you build products that depend on advanced chips—AI workloads, edge devices, consumer hardware, or even data-center capacity planning—lithography constraints eventually become planning constraints: price swings, lead times, and node availability can influence what you ship and when.
In practice, many teams respond by building lightweight internal tools: dashboards that track supplier signals, models that estimate BOM sensitivity, or simple apps that coordinate procurement, deployment, and forecasts across teams.
Platforms like Koder.ai can help here because they let you create web apps, backends, and even mobile apps from a chat-driven workflow—useful when you need a functional internal tool quickly without spinning up a full traditional development pipeline. For example, a small operations team can prototype a React-based dashboard with a Go + PostgreSQL backend, iterate in “planning mode,” and keep changes safe with snapshots and rollback.
Building EUV lithography isn’t like copying a single machine. It’s the result of decades of iteration across optics, vacuum systems, light sources, metrology, software, and materials—and all of those pieces must work together at production speed with extreme reliability.
Time is the first barrier: EUV required long, expensive learning loops where each generation taught the next. The second is the ecosystem: critical subsystems come from specialized suppliers with deep expertise and long qualification histories. Patents and proprietary know-how matter too, but the bigger hurdle is manufacturing experience: getting a system to print consistently on real wafers, day after day, and then supporting it worldwide.
No. EUV is used for layers where the smallest features matter most, but DUV still prints many layers even in advanced chips.
Fabs mix EUV and DUV because different layers have different requirements (resolution, throughput, cost, maturity). DUV also remains essential for many products where EUV isn’t economically justified.
Also no. ASML is a major gatekeeper for leading-edge chips because EUV tools are scarce, complex, and slow to build. But chip output depends on much more: photoresist chemistry, photomasks, wafer supply, inspection tools, packaging capacity, and skilled engineers to run and maintain the process.
EUV lithography is hard because physics is unforgiving and manufacturing tolerances are extreme. Progress is limited by the entire chip supply chain, not one company alone—yet EUV tool availability strongly shapes who can build the most advanced chips.
Going forward, watch High-NA EUV rollouts, improvements in resist and mask technology, and how export controls and capacity expansion affect who gets access to the next wave of leading-edge production.
Lithography is the “pattern printing” step in chipmaking. Light projects a pattern from a photomask onto a photoresist-coated wafer, then the wafer is developed and etched/deposited so the pattern becomes real structures.
Because every layer must align precisely, small errors in focus, overlay (alignment), or uniformity can reduce yield or performance.
For the most advanced process nodes, EUV lithography is a key capability that’s hard to replace with other methods at scale. ASML’s tools concentrate that capability, so access to their scanners strongly influences who can manufacture leading-edge chips efficiently.
“Gatekeeper” doesn’t mean ASML controls everything—just that at the frontier, progress is constrained by this specific tool class and its availability.
DUV (deep ultraviolet) lithography typically uses 193 nm light and is still widely used across many layers because it’s mature and fast.
EUV (extreme ultraviolet) uses 13.5 nm light, which can print finer features more directly. The main practical win is reducing the need for complex multi-patterning on critical layers at the leading edge.
Multi-patterning is splitting one intended layer into multiple mask/exposure/etch cycles to mimic smaller feature printing when a single exposure can’t do it reliably.
It works, but it adds:
EUV tools are difficult because EUV light is absorbed by air and most materials, so the system must operate in vacuum and use mirrors instead of lenses. Generating EUV light reliably is also a major engineering challenge.
On top of that, tiny contamination can degrade mirrors and throughput, so cleanliness and defect control are unusually strict.
At a high level, an EUV scanner integrates:
The value comes from the system working reliably together at production uptime—not just one breakthrough component.
They depend on EUV for the tightest, most critical layers in leading-edge nodes, while still using plenty of DUV for other layers.
In practice, fabs plan EUV capacity years ahead because tool delivery, fab readiness (utilities, vibration control, cleanroom integration), and process maturity (masks/resist/metrology) must all line up.
EUV access is highly concentrated, and the tools can determine whether a region can manufacture the most advanced chips at scale. That makes EUV a strategic chokepoint.
Export controls can restrict shipments to certain destinations or end uses, which can shift where capacity is built and add uncertainty to long-range fab planning.
The price reflects extreme precision, low production volume, long test/qualification cycles, and specialized parts (optics, stages, vacuum, light source). But the sticker price is only part of the story.
Fabs focus on total cost of ownership:
A small availability drop can materially reduce wafer output.
High-NA EUV increases numerical aperture (NA), enabling finer patterning and potentially fewer workarounds at the smallest features.
It won’t be a simple switch because resists, masks, inspection, and throughput must mature together. Expect gradual adoption and mixed fleets (High-NA EUV + “standard” EUV + DUV) for many years.